The present invention relates to a video image processing circuit and, more particularly, to a video image processing circuit including an image detection circuit of synchronous detection type.
In TV receivers, the gains of the tuner and the intermediate frequency amplifier circuit (referred to as IF amplifier) are controlled automatically in accordance with the level of the output from the image detection circuit which receives the output from the IF amplifer, i.e. with the level of the video signal. Consequently, the video detection circuit produces output video signal of a substantially constant level, in spite of possible change of the intensity of the received signal.
The video detection circuit of synchronous type is superior to the diode type detection circuit, because it provides better linearity and, accordingly, exhibits better detection characteristics even for a low level of the input signal, as compared with the diode type detection circuit. In addition, the synchronous type picture detection circuit poses a relatively small load to the IF amplifier. For these reasons, the synchronous type picture detection circuit can easily be formed as a semiconductor integrated circuit (referred to as IC) in combination with, for example, the IF amplifier.
However, it has been proven as a result of experiments that this synchronous type detection circuit poses a problem as stated below. Namely, when a channel of large electric field strength is selected after a switching of the channel or after turning the power switch on or off, the level of the detection signal of the video detection circuit is changed substantially to zero, although the channel is correctly selected, so that the automatic gain control signal (referred to as the AGC signal) to be delivered to the tuner and the IF amplifier is inconveniently held at such a level as to lock the circuit in full gain condition.